Balanced inductor
US6320491A · kind A · utility
14Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2000 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Mar 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F2017/0073
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A balanced inductor formed on lossy substrate material having adjacent strips leading current in opposite directions and being arranged in such a way that substrate currents relating to individual strips (1) induced in the lossy substrate (3) are balancing out one another leading to high Q-values. The inductor structure according to the invention can be implemented in MMIC devices using standard semiconductor substrates and do not require any special treatment of the substrate being needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.