Circuit and method for generating pixel data elements from analog image data and associated synchronization signals
US6320574A · kind A · utility
18Cited by
30References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 20, 1998 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | May 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.