Method, architecture and circuit for locking a data transmission frame
US6320881A · kind A · utility
0Cited by
8References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 25, 1998 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Jun 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/426
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprising a first counter, a second counter, a third counter and a decoder, where the decoder may be configured to present a locked output signal. The first counter may present a first output signal in response to a start of frame signal and one or more control signals. The second counter may be configured to present a second output signal in response to the start of frame signal and the first output signal. The third counter may present a tracking control signal to the first counter in response to one or more of the control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.