Method and apparatus for integrated circuit design verification
US6321186A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1999 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | May 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for verifying an integrated circuit design using constraint information to develop a weighted data structure. In one embodiment, a binary decision diagram (BDD) includes a plurality of nodes (401, 402, 403, 404, 405, 406, 407, 420, and 430) representing signals and states in the circuit, and each node has a branching probability based on user-defined weights. The BDD represents the intersection of the input space and state space which satisfies the constraints. Current state information resulting from simulation is used to dynamically adjust the branching probabilities of the BDD on the fly. In one embodiment, the constraint information is applicable for formal verification of a portion of the circuit. In another embodiment, a simulation controller (12) receives design and constraint information and generates the program to control simulator (14).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.