Memory arbitration scheme with circular sequence register
US6321309A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1999 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | May 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for arbitrating between requests from a plurality of sources for access to a shared resource, the apparatus comprising: PA1 a register means having a plurality of stages, each stage containing a designation of one of said sources, a plurality of stages containing a designation of the same source, PA1 logic means for accessing the register stages according to a priority scheme and for comparing the designation in each stage with requests for access, and granting access according to the match between the highest priority source designation and a memory request, and means for changing the contents of the register means subsequent to access grant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.