Executing debug instructions
US6321329A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1999 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | May 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for processing data is provided, said apparatus comprising: a main processor 4 driven by a main processor clock signal clk at a main processor clock frequency; debug logic 6, 12 at least a portion 12 of which is driven by a debug clock signal tck at a debug clock frequency, said debug clock frequency being different to said main processor clock frequency and said main processor clock signal clk being asynchronous with said debug clock signal tck; and an instruction transfer register ITR into which a data processing instruction may be transferred by said debug logic 12 and from which said data processing instruction may be read by said main processor 4; wherein when switched from a normal mode to a debug mode said main processor 4 continues to be driven by said main processor clock signal clk executing no-operation instructions until a data processing instruction is present within said instruction transfer register ITR and said debug logic 12 triggers said main processor to read and execute said data processing instruction whilst still driven by said main processor clock signal clk. This arrangement allows debug instructions to be executed at full speed whilst avoiding the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.