MISFET semiconductor device having relative impurity concentration levels between layers
US6323525A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1998 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Sep 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6721
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a MISFET with an EV source/drain structure has a gate electrode formed on part of a first p-type semiconductor layer via a gate insulating film. A second n.sup.+ -type semiconductor layer is formed in the prospective source and drain regions of the first semiconductor layer via the gate electrode, and a third n.sup.- -type semiconductor layer is formed on the second semiconductor layer. Each of source and drain regions is formed from the second and third semiconductor layers. The upper edge of the source/drain regions is formed above the boundary between the first semiconductor layer and the gate insulating film. In an ON state, part of a depletion layer in the drain region is formed in the third semiconductor layer, and part of a depletion layer in the source region is formed in the second semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.