Programmable logic device configured to accommodate multiplication
US6323680A · kind A · utility
105Cited by
26References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2000 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Mar 2, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device is configured to accommodate multiplication by the provision in each logic region of specialized components to form and sum partial products. The specialized components are separate from the ordinary logic of the logic region, and their presence imposes little penalty on the performance of ordinary logic functions, while enhancing the speed at which multiplication is performed by minimizing the number of logic regions used for a particular multiplication operation, and also minimizing the use of the interconnection resources of the device to convey signals among those regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.