Low distortion sample and hold circuit
US6323697A · kind A · utility
31Cited by
2References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2000 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Jun 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit 100, which can be used to perform a sample and hold function, includes a switch 112 with a current patch coupled between an input node VIN and an output node VOUT. A capacitor 114 is coupled to the output node VOUT. A replica device 160 includes a current path coupled between the input node VIN and a supply voltage node VDD. A bootstrap circuit, e.g., including a bootstrap capacitor 164, is coupled between a control terminal of the first switch 112 and a control terminal of the replica device 160.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.