System and method for deskewing synchronous clocks in a very large scale integrated circuit
US6323714A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2000 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Feb 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for actively deskewing synchronous clocks in a VLSI circuit by introducing a controllable delay unit within a local clock buffer within each of a number of circuit zones and applying a controllable delay at each of the local clock buffers in response to a phase comparison of clock signals from one or more adjacent clock zones. The system can be added to any of a number of various clock distribution networks on a VLSI circuit through the introduction of controllable clock zone buffers and localized phase comparators. By adjusting each localized clock buffer delay unit in response to measured clock signal phase differences from adjacent circuit zones, clock skew problems can be minimized across various clock zones on a VLSI circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.