Control systems and methods for reducing residue signal offset in subranging analog-to-digital converters
US6323791A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1999 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Oct 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Feedback control systems and methods are provided for correcting residue signal offset errors in subranging ADCs. The systems and methods eliminate clock-to-clock offset changes and reduce noise generation. An exemplary control system includes a feedback loop around a residue sampler and a residue amplifier that includes a) a feedback sampler that resamples the output signal of the residue sampler to produce a resampled residue signal, and b) an offset current generator that delivers an offset current to the residue amplifier with a current magnitude that is responsive to the resampled residue signal. The sampling of the residue and feedback samplers is time shifted to block the propagation of spurious signals that are typically generated in DACs of the subranging structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.