Reading circuit for nonvolatile memory cells without limitation of the supply voltage
US6324098A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2000 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Apr 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reading circuit for nonvolatile memory cells, including a current-to-voltage converter, having an array load, connected to a memory cell, and a reference load connected to a reference generator. The array load and the reference load include PMOS transistors presenting an array shape factor (W/L).sub.F and, respectively, a reference shape factor (W/L).sub.R. The reading circuit further includes a charge pump that supplies a biasing voltage to a gate terminal of the memory cell. The biasing voltage is proportional to and higher than a supply voltage V.sub.DD. The ratio between the array shape factor (W/L).sub.F and the reference shape factor (W/L).sub.R is a non-integer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.