Instruction converting apparatus using parallel execution code
US6324639A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1999 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Mar 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1.sup.th unit field in the parallel execution code, and the long instruction is assigned to the s.sup.th unit field to the (s+k-1).sup.th unit field in the same parallel execution code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.