Asynchronous switching circuit for multiple indeterminate bursting clocks
US6324652A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1999 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Jan 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronous switching circuit for multiple indeterminate bursting clocks. In one embodiment, the present invention recites a clock-switching circuit that provides a single unclipped and glitch-free clock signal at its output from among multiple clock inputs. The clock-switching circuit is comprised of a plurality of asynchronously-enabled clock circuits, a plurality of blocking circuits, a synchronizing clock, and a logic gate. Each of the plurality of blocking circuits has an input lead respectively coupled to one of the plurality of asynchronously-enabled clock circuits, each of the plurality of blocking circuits also has an output coupled to all of the plurality of asynchronously-enabled clock circuits except the one to which its input is coupled. The synchronizing clock is coupled to each of the plurality of blocking circuits while the logic gate is coupled to each of the plurality of asynchronously-enabled clock circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.