Charge balance type photodiode array comprising a compensation circuit
US6326603A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 9, 1999 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Sep 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/57
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In order to improve the noise performance of a charge balance type photodiode array by reducing error influences, e.g. due to offset voltages, flicker and/or thermal noise, on a desired signal a compensation circuit is inserted in each channel of this array. The basic concept under lying this compensation circuit is to effect a correlated double sampling method without any significant increase in space or power demand for the silicon chip of at least one channel of said photodiode array. Because the wanted signal is primarily an amount of charge, the compensating circuit comprises a switchable compensating capacitor to compensate an error contribution of the desired signal. In a first "calibration period" the compensating capacitor is charged or discharged in dependence on the actual noise contribution. In a second compensation period the compensation capacitor provides a voltage which is used to correct a predetermined reference voltage to insure compensation of the error contribution. These periods are synchronized to the charge balance technique used in connection with the photodiode array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.