Method of analyzing semiconductor surface with patterned feature using line width metrology
US6326618A · kind A · utility
13Cited by
14References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1999 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Jul 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/2814
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of analyzing a patterned feature formed on a semiconductor layer is disclosed. The patterned feature is scanned to generate an amplitude modulated waveform signal of the line width. This waveform signal is processed for calculating the scale and shape of the patterned feature based on the profile of the amplitude modulated waveform signal. The calculated scale and shape of the patterned feature are compared to a template of a normal patterned feature having the desired shape and scale. The template is derived from scanning a normal patterned feature on a known sample.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.