Full swing power down buffer with multiple power supply isolation for standard CMOS processes
US6326832A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2000 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Mar 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer circuit includes a pull-up output transistor formed in a well, the well isolated from the power supply only when a voltage exceeding the power supply voltage appears on the buffer output node. Isolation of the well is accomplished by linking the well to the power supply through an isolation transistor, such that the control node of the isolation transistor receives the output of a switching inverter utilizing the buffer output voltage as its high power rail. During normal operation, the output voltage is less than the power supply voltage and thus the output of the switching inverter is low. As a result, the isolation transistor is activated, and the well is pulled up to the power supply voltage. Appearance of a voltage greater than the circuit power supply on the buffer output node activates the switching inverter, raising the control voltage and deactivating the isolation transistor. In this manner, the well is isolated from the power supply rail. The buffer circuit further includes transmission gates positioned between the buffer input node and the output pull-down transistor. These transmission gates are controlled by the control voltage output by the switching…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.