Isolated reference bias generator with reduced error due to parasitics
US6326836A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1999 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Sep 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/205
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A bias circuit with an input current having a first reference node, the input current being gain divided to form a current smaller than the input current by a magnitude of the gain. The gain divided current being transferred through an intermediate current mirror with optional gain and to provide an output current. The output may have a second reference node that is different in voltage to the reference node of the input current, and multiplies the gain divided current by a gain so that the output current has a value equal to or greater than, but proportional to, the input current whereby an impedance in the output reference node is not reflected back.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.