Circuitry, architecture and method(s) for phase matching and/or reducing load capacitance, current and/or power consumption in an oscillator
US6326853A · kind A · utility
4Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1999 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Aug 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of clock signals each in response to (i) one or more control inputs and (ii) one or more of a plurality of phase timing elements. The second circuit may be configured to generate the plurality of phase timing elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.