Electrostatic discharge circuit

US6327126A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• James W. Miller · Austin, US
• Michael G. Khazhinsky · Austin, US
• Geoffrey B. Hall · Austin, US
• Jose A. Camarena · Austin, US
• Joseph Chan · San Francisco, US
• Fujio Takeda · Austin, US

Key dates

• Filing date: Jan 28, 2000
• Grant date: Dec 4, 2001
• Expiry date: Jan 28, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/601

Abstract

A circuit (600) provides Electrostatic Discharge (ESD) protection for internal elements in an integrated circuit during an ESD event. The circuit (600) includes cascoded NMOSFETs (614, 616), with the upper NMOSFET (614) connected to voltage divider circuitry (628). The voltage divider circuitry (628) provides a first bias voltage to the gate of the upper NMOSFET (614) during an ESD event and a second bias voltage during normal operation. Preferably, the first bias voltage is approximately 1/2 of the drain voltage of the upper NMOSFET (614). Under these bias conditions the cascoded NMOSFETs exhibit a maximum voltage threshold for initiation of parasitic lateral bipolar conduction.