Single event upset (SEU) hardened latch circuit
US6327176A · kind A · utility
37Cited by
5References
25Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Apr 26, 2001 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Apr 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single event upset hardened latch circuit is disclosed. The single event hardened latch circuit includes a first dual-port inverter and a second dual-port inverter. An input is coupled to the first dual-port inverter via a first set of pass gates. The first dual-port inverter is coupled to the second dual-port inverter via a second set of pass gates. The output is connected to the first and second dual-port inverters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.