Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding
US6327207A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2001 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Apr 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital logic circuit, such as a FIFO memory includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain. Each pointer is encoded with a "2-hot" encoded value within one of the clock domains. The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain. Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.