Method for creating a simulation environment for enhanced logic verification of a branch history table
US6327559A · kind A · utility
8Cited by
5References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 4, 1999 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | May 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for creating a verification environment to drive a Branch History Table. It consists of two components. First, a method for creating instruction streams for controlling the stress on branch history table logic. The second is a method for pre-loading the branch history array to allow for interesting simulations at the beginning of the test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.