Translation look-aside buffer utilizing high-order bits for fast access
US6327646A · kind A · utility
22Cited by
6References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 12, 1999 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Mar 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast translation look-aside buffer for translating a linear address R.sub.L =A+B to a physical address, where A and B are two N bit operands. Inputs to the translation look-aside buffer are the n highest-order bits of A and B, where n<N, and the carry-out term from the sum of the first N-n bits of A and B. The TLB may provide a hit without the need for the sum of A and B.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.