Semiconductor integrated circuit for cryptographic process and encryption algorithm alternating method
US6327654A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1998 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Sep 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit for cryptographic process according to the present invention, comprises a randomizing unit for randomizing first input data which is one of two divided parts of input data based on configuration information to identify an algorithm in randomizing process, a function F portion for receiving data which have been subjected to the randomizing process and then applying coding process to the data, and an exclusive logical sum circuit for receiving second input data which is other of two divided parts of the input data and output data from the function F portion and then outputting an exclusive logical sum of the second input data and the output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.