Analog-to-digital converter and method of fabrication
US6329260A · kind A · utility
15Cited by
45References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Sep 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.