Slope and level trim DAC for voltage reference
US6329804A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Oct 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/30
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method and apparatus for trimming the level and slope in a voltage reference using current-switching DACs to inject small correction currents into or draw currents from the voltage reference circuit. Each DAC is controlled via a programmable non-volatile memory, which can be programmed after final packaging. Thus, the present technique enables trimming the voltage reference circuit after the circuit has been packaged. For the slope trim, the current is injected into or drawn from one side or the other of the band-gap core cell. The level trim DAC sources a correction current into or sinks a correction current from the resistor chain that sets the voltage level at the base of the transistors in the band-gap core. The level and slope trim DACs generate currents that are precise multiples of the currents through the resistors being trimmed. Thus the corrections are invariant with process and temperature, the necessary trim range is minimized, and the shape of the remaining error (curvature) is not altered. This current replication technique has the same effect as an ideal trim, i.e. produces the same result as changing the values of the resistors around which the trim circuits are p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.