Quiet output buffers with neighbor sensing of wide bus and control signals
US6329835A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2000 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Feb 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00346
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer has a large pull-down driver transistor that draws a large current. The large driver transistor is pulsed off when a neighboring pin is switching, reducing noise and ground bounce. Pulse signals and a local enable are NOR'ed together to drive the gate of the large driver. The pulse signals are routed to many output buffers in a chip. Each data input is sent to a detector slice. The detector slice normally generates a pulse when the data input changes. These pulses from individual detector slices are combined into the pulse signals. The detector slice also receives a control signal from a control input to the chip. The control input enables a latch or flip-flop in the data path from the data input to the output buffer. When the latch is enabled, changes in the data input do not immediately affect the output buffer, but must wait for a clock edge. The control input that enables the latch also controls a mux in each detector slice. The mux disables the bit slice from generating a pulse when the data input changes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.