Logic gate cell
US6329845A · kind A · utility
13Cited by
5References
59Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 15, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Jun 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
To provide a small-area and low-power-consuming logic gate cell which is constructed of a circuit of two inverting logic gates connected in series in a layout of four-step diffusion regions. A first inverting logic gate is formed of a small transistor on internal two-step diffusion regions, a second inverting logic gate is formed of external two-step diffusion regions, and output wirings of the second inverting logic gate is formed of second metal layer wirings so that the second metal layer wirings extend over the first inverting logic gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.