Phase locked loop integrated circuits having dynamic phase locking characteristics and methods of operating same
US6329854A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Aug 31, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/107
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Phase locked loop integrated circuits include a phase detection circuit, a variable delay device and a delay control circuit. The variable delay device and delay control circuit provide improved characteristics by increasing the signal frequency bandwidth of the delay locked loop integrated circuit in a preferred manner. The phase detection circuit is configured to perform the functions of comparing first and second periodic signals and generating a phase control signal (e.g., VCON) having a first property (e.g., magnitude) that is proportional to a difference in phase between the first and second periodic signals. The delay control circuit is responsive to the phase control signal VCON and generates a delay control signal that is provided to the variable delay device. The delay control circuit may comprise a counter, a first comparator, a second comparator and a shift register. The variable delay device includes a variable delay line and a compensation delay device. The variable delay line may contain a string of unit delay devices and a string of switches that each have an input electrically coupled to an output of a corresponding unit delay device. Each of the unit delay devices…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.