Nonvolatile semiconductor memory device
US6330189A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2000 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Aug 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In NAND type EEPROM capable of high-speed rewriting by ensuring that the memory cell current during write verify read-out operation is larger than that during normal data read-out operation, a NAND cell is composed of a plurality of serially connected memory cells (MC0 through MC31) and selection transistors (SST and GST). During data write operation, a voltage (Vpgm) is applied to a selected word line of a selected block, and a pass voltage (Vpass2) is applied to non-selected word lines to introduce electrons to the floating gate of the selected memory cell. In verify read-out operation after data write operation, a verify read-out voltage is applied to the selected word line and a pass voltage (Vpass3) to non-selected word lines. The pass voltage (Vpass3) applied to non-selected word lines during verify read-operation is higher than the pass voltage (Vpass1) applied to non-selected word lines during normal data read-out operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.