Digital channelizer having efficient architecture for window presum using distributed arithmetic for providing window presum calculations in one clock cycle
US6330287A · kind A · utility
3Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Feb 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital channelizer and a process for dividing input bandwidth into at least some of N channels are disclosed. The digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes an analog to digital converter (14), a demodulator (16) coupled to the analog to digital converter, a window presum (102) coupled to the parallel streams of data words and a discrete Fourier transform apparatus (26'), coupled to the N outputs of the window presum, having N inputs and which performs a discrete Fourier transform on the N inputs to output at least some of the N channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.