Merge sorting apparatus with comparison nodes connected in tournament tree shape
US6330559A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 11, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Jun 11, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99937
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A merge sorting apparatus includes a comparison tournament circuit including comparison nodes, and a comparison control circuit for supplying to the corresponding comparison nodes validity flag information concerning the input data to each of the comparison nodes determined based on comparison results from the comparison nodes. The comparison control circuit includes comparison result registers for retaining the comparison results, validity flag registers for retaining the validity flag information, and merge member registers for retaining information as to whether the input data to each of the input registers corresponding to respective pathways should be the object of comparison in the following data comparison processing. With this arrangement, contending readouts of record arrays from a memory can be reduced and the necessity to initialize each register is eliminated, thereby speeding merge sorting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.