High speed serial line transceivers integrated into a cache controller to support coherent memory transactions in a loosely coupled network
US6330591A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1998 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Mar 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more improved transmit units tightly integrated into an enhanced cluster cache with controller. Coherent memory transactions in a loosely coupled computer network are supported by sending all cache updates to all computers in the loosely coupled computer network through high speed, low latency and high bandwidth serial lines linking all computers to all other computers. The cluster cache controller may include a local cache controller and/or as a local bus controller. The local bus controller is operable to coupled the cluster cache to an I/O subsystem. A local cache memory preferably caches data and/or instructions, or locations thereof for the entire computer, making the local computer cache available to the entire computer cluster through the transmit unit. Each transfer unit is a full-duplex transceiver that includes transmitter and receiver functions. Each transfer unit can send and receive data simultaneously since operation of their transmitter and receiver functions are independent. Each transmit unit comprises a receiver operably coupled between an input port and an output port, and a timing generator coupled to recover a clock signal from the serialized data and to…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.