Systems and methods for a disk controller memory architecture
US6330626A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2000 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Apr 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0674
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is related to systems and methods for a disk controller memory. In one embodiment, a mass storage device is interfaced to a computer via an I/O bus using a mass storage device controller. The mass storage device controller includes a processor and a buffer memory configured to receive data from the mass storage device and the I/O bus. In addition, the controller includes a memory circuit coupled to the buffer memory and the processor. The memory circuit is configured to operate as a first-in-first-out memory during at least a first transfer of data between the memory circuit and the buffer memory. For example, the memory may be configured to operate as either as a random access memory or a FIFO during at least a first transfer of data between the memory circuit and the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.