Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures
US6330662A · kind A · utility
40Cited by
6References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 23, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Feb 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction fetch unit for fetching instructions from an instruction cache of a processor. The fetch unit includes a next fetch address mechanism generating predicted next fetch addresses, the next fetch address mechanism generating a next fetch address for a fetch bundle over at least two cycles of the processor. The next fetch address mechanism determines the next fetch address based on whether a control transfer instruction from an intermediate set of fetched instructions is taken.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.