Hamming value determination and comparison
US6330702A · kind A · utility
6Cited by
7References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 10, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Aug 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/165
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The comparators described herein comprise bit manipulation cells of a number of logic cells each built up of AND, OR etc. logic gates interconnected in parallel to make up one or more layers and do not rely on clocks, instead operating asynchronously. This makes the comparators highly robust and fault tolerant, and well suited for use as binary neurons in high integrity systems. They are less susceptible to radio frequency interference induced data corruption than alternative register-based implementations. Planar Hamming comparators capable of comparing two dimensional input arrays are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.