Secure programmable logic device
US6331784A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2000 |
| Grant date | Dec 18, 2001 |
| Priority date | — |
| Expiry date | Jul 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic chip and configuration memory chip are mounted within a multi-chip module to form a single package. The configuration memory has a security bit which in a first state allows programming and read-back of configuration data in the memory chip via external pins of the package, and in a second state allows only erase command to be communicated to the memory chip via the external pins. The internal data transfer connection between the memory chip and programmable logic chip is enabled when the security bit is in the second state and the memory chip is in a read-back mode, allowing configuration data to be loaded into the logic chip upon power up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.