Highly linear sigma-delta modulator having graceful degradation of signal-to-noise ratio in overload condition
US6331833A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2000 |
| Grant date | Dec 18, 2001 |
| Priority date | — |
| Expiry date | Jan 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-bit analog-to-digital converter architecture, which during normal operation behaves like a single-bit converter, thus sharing the high linearity and low distortion properties of the simpler system. When a high input signal is applied, a second bit is triggered and the system behaves like a more complex multi-bit system, providing system stability where a single-bit comparator would overload and the system would become unstable. During normal operation, a single-bit converter is sufficient to stabilize the system. When the input is a large, sustained signal (relative to the full scale of the converter) this single-bit approach is not sufficient to maintain system stability. Thus, if the input to the analog-to-digital converter is close to its maximum or minimum range (implying a large positive or negative input signal) a second bit is triggered, providing stable linearity where the signal-to-noise ratio of a conventional sigma-delta converter would rapidly drop off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.