Semiconductor memory device and control method thereof
US6331959A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2000 |
| Grant date | Dec 18, 2001 |
| Priority date | — |
| Expiry date | Mar 14, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storage device is disclosed that can lower sense amplifier input potentials to about a half supply potential (VCC/2) to speed up sense amplifier operations. According to one embodiment, a semiconductor storage device (100) may include a pair of digit lines (104 and 106), a memory cell (108) that can place stored data on digit lines (104 and 106), a sense amplifier (112) that may read memory cell data on digit lines (104 and 106), and switching devices (120-a and 120-b) connected between sense amplifier inputs (112-a and 112-b) and digit lines (104 and 106). Digit lines (104 and 106) may be precharged to a high potential. Memory cell data may then be placed on the digit lines (104 and 106). Prior to the activation of the sense amplifier (112) switching devices (120-a and 120-b) may lower the digit line potentials to a level more conducive to sensing by the sense amplifier (112). In this way, a read operation by the sense amplifier (112) may be faster than conventional approaches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.