Digital signal processor with bit FIFO
US6332188A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1998 |
| Grant date | Dec 18, 2001 |
| Priority date | — |
| Expiry date | Nov 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30101
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at least one control information register for storing control information used by the bit transfer mechanism.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.