Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array
US6333641A · kind A · utility
9Cited by
14References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 5, 2000 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | May 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device includes an array of logic modules. A standard interconnection grid, with vertical routing lines, horizontal routing lines, and local routing lines, links the array of logic modules. An omniversal bus is positioned over the array of logic modules. The array of logic modules includes selective links to the omniversal bus, such that the omniversal bus dynamically establishes autonomous sub-arrays of logic modules of variable size attached to the omniversal bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.