Phase locked loop arrangement in which VCO frequency is a fraction of reference frequency
US6333679A · kind A · utility
6Cited by
5References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 9, 2000 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Jun 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a phase locked loop arrangement of a frequency synthesiser, a signal outputted from a voltage controlled oscillator is locked to a reference oscillator. A phase detector is arranged so that the frequency of the reference oscillator is a multiple of the frequency of the voltage controlled oscillator, which significantly reduces the phase noise emitted by the voltage controlled oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.