Semiconductor device operable in a plurality of test operation modes
US6333879A · kind A · utility
24Cited by
10References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 1999 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Jan 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit generating a test mode instructing signal includes a test mode register circuit which is set to a state disabling instruction of a test mode in a standby state. An intended test mode can be accurately selected even when the test mode is instructed in accordance with a plurality of external signals varied in timing from each other. A semiconductor device allows accurate and efficient execution of the test without requiring increase in area occupied by an array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.