On-line line monitor system
US6333915A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1998 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Jul 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/6402
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An on-line line monitor system is provided for fault diagnosis of signal processing blocks, which perform cross-connecting of ATM cells by using at least reception-side memory blocks, a SRAM block and transmission-side memory blocks under control of a CPU block with respect to an operating line system, which is presently placed in an on-line state to be in communication service, and a spare line system which is placed in a standby state to be out of the communication service. Test ATM cells are sequentially input to the signal processing blocks, in which they are processed and are then output together with normal ATM cells. By comparing the processed test ATM cell with the original test ATM cell, it is possible to determine occurrence of fault in the signal processing blocks. When the fault is detected with respect to the operating line system, line control is switched over to the spare line system. In addition, the on-line line monitor system monitors a pileup state of the normal ATM cells in the SRAM block. So, a rate of the test ATM cells to be sequentially input to the signal processing blocks is adjusted in response to the pileup state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.