System and method for memory self-timed refresh for reduced power consumption
US6334167A · kind A · utility
37Cited by
34References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1998 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Aug 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40615
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller, upon detecting an interval of inactivity (that is, no read or write access from a processor or I/O devices with respect to main storage or memory SDRAMs) halts external refresh commands from the processor, and initiates STR mode in main storage to preserve data contents in the memory SDRAMs and to save energy. Then, upon detecting a read or write operation, the memory controller signals main storage to exit STR mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.