DSP coprocessor having control flags mapped to a dual port section of memory for communicating with the host
US6334179A · kind A · utility
5Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1999 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Jan 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DSP coprocessor 2 is connected to a host sub-system (3). The host sub-system (3) has a host processor (4), a host RAM (5), and shared RAM banks (6, 7). Multiplexers (11) provide access for either the DSP or the host to a shared RAM bank. Macro commands for functions of the DSP coprocessor are retrieved from the shared RAM banks. This allows comprehensive interaction of the host and the DSP coprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.