Method of fabricating a lead-on-chip (LOC) semiconductor device
US6335227B1 · kind B1 · utility
2Cited by
6References
8Claims
0Family size
Inventors
Key dates
| Filing date | Oct 18, 2000 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Oct 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.