Semiconductor device having a mark section and a dummy pattern
US6335560B1 · kind B1 · utility
30Cited by
1References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 9, 1999 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Dec 9, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of real chip regions and dicing lines to separate the real chip regions on a semiconductor substrate. A dicing line includes a mark section and a mark forbidden region around the mark section. A dummy wiring pattern is formed to fill the dicing line or a portion of the real chip region to surround the mark section and the mark forbidden region. A dummy wiring pattern may be a single continuous wiring pattern or the single wiring pattern may be divided into segments. Alternatively, a dummy wiring pattern may be composed of a plurality of square portions arranged in a matrix fashion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.