Method and design for the suppression of single event upset failures in digital circuits made from GaAs and related compounds
US6335562B1 · kind B1 · utility
3Cited by
14References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1999 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Dec 9, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/958
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Single event upset failure are suppressed in GaAs-based electronics by implanting the GaAs substrate with an appropriate dose of O and at least one of either Al, Cr, or In.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.